The Zilog Z80 Processor

Zilog Z80 This is a page about my first favorite microprocessor that I worked with, the Z80 processor. When I was twenty years old in 1979 I bought my first real computer, the Tandy TRS-80 model I level II with a Z80 processor at its heart. In no time I was able to program in assembler for this and I wrote complex assembler programs and utilities for the Z80 processor. All computers I bought after that had a Z80 processor like the Sinclair Spectrum and later the MSX. After My first job was developing hardware and software on embedded Z80 systems (cash register and machine control systems) in assembler and PL/Z. After that I started working at Micro Technology (an MSX hardware supplier) and again I was programming assembler using the Z80 but the I also learned to program in ‘C’. After that the 8031 processor became my second love and I then I started to write assembly for the 8086 and 80186 processor. I have been an embedded programmer until 1999 when I switched to Internet programming. After many years I picked up the Z80 again and on this page you can find information about old and new Z80 projects and find the documentation. The Z80 was a genius design for its time and its funny that this processor is still used and available.
Regards, Hein Pragt.

I also have a Facebook Group on Retro Computing and Electronics, feel frtee to join!

About the Zilog Z80

Zilog Z80 chip

The Z80 was developed by Federico Faggin who had been working at Fairchild Semiconductor and later at Intel on fundamental transistor and semiconductor manufacturing technology. He had been working on the Intel 4004 and 8080 processor and several other ICs. Masatoshi Shima, the principal logic and transistor level-designer of the 4004 and the 8080. The first working samples of the Z80 processor were delivered in March 1976, and it was officially introduced on the market in July 1976. They also developed assembler based development systems and some peripheral ICs to build computer systems with a low number of chips. A good move was that Faggin designed the instruction set to be binary compatible with the Intel 8080 processor so that most 8080 code would run unmodified on the new Z80 CPU. But he Z80 had a lot of extensions to the 8080 processor and became very popular. A lot of companies took a license and the Z80 processor (and support chips) were manufactured by many companies. Beside the single 5V power the built-in DRAM refresh that made computer systems cheaper with larger memory because dynamic ram chips were much simpler, a lot of ram element could be packed in a single chip and the price per bit was very low compared to static ram chips.

Z80 40 pins DIL pins

The most handy version of the Z80 processor to me is still the 40 pins DIL Z80 version, it's easy to solder into a board and the pins are big enough for the clips of measuring devices.

[ins of the z80 cpu

Z80 pin functions

  • A15–A0. Address Bus (output, active High, tristate). A15–A0 form a 16-bit Address Bus, which provides the addresses for memory data bus (up to 64 KB) and for I/O device addressing.
  • BUSACK. Bus Acknowledge (output, active Low). Bus Acknowledge indicates to the requesting device that the CPU address bus, data bus, and control signals MREQ, IORQ, D, and WR have entered their high-impedance states. The external circuitry can now control these lines.
  • BUSREQ. Bus Request (input, active Low). BUSREQ forces the CPU address bus, data bus, and control signals MREQ, IORQ, RD, and WR to enter a high-impedance state so that other devices can control these lines. BUSREQ is normally wired OR and requires an external pull-up for these applications.
  • HALT indicates that the CPU has executed a HALT instruction and is waiting for either a nonmaskable or a maskable interrupt (with the mask enabled) before operation can resume. During HALT, the CPU executes NOPs to maintain memory refreshes.
  • INT. Interrupt Request (input, active Low). An Interrupt Request is generated by I/O devices. The CPU honors a request at the end of the current instruction if the internal software-controlled interrupt enable flip-flop (IFF) is enabled.
  • D7–D0. Data Bus (input/output, active High, tristate). D7–D0 constitute an 8-bit bidirectional data bus, used for data exchanges with memory and I/O.
  • IORQ. Input/Output Request (output, active Low, tristate). IORQ indicates that the lower half of the address bus holds a valid I/O address for an I/O read or write operation. IORQ is also generated concurrently with M1 during an interrupt acknowledge cycle to indicate that an interrupt response vector can be placed on the data bus.
  • M1. Machine Cycle One (output, active Low). M1, together with MREQ, indicates that the current machine cycle is the op code fetch cycle of an instruction execution. M1, when operating together with IORQ, indicates an interrupt acknowledge cycle.
  • MREQ. Memory Request (output, active Low, tristate). MREQ indicates that the address bus holds a valid address for a memory read or a memory write operation.
  • NMI. Nonmaskable Interrupt (input, negative edge-triggered). NMI contains a higher priority than INT. NMI is always recognized at the end of the current instruction, independent of the status of the interrupt enable flip-flop, and automatically forces the CPU to restart at location 0066h.
  • RD. Read (output, active Low, tristate). RD indicates that the CPU wants to read data from memory or an I/O device. The addressed I/O device or memory should use this signal to gate data onto the CPU data bus.
  • RESET. Reset (input, active Low). RESET initializes the CPU, during reset time, the address and data bus enter a high-impedance state, and all control output signals enter an inactive state. RESET must be active for a minimum of three full clock cycles before a reset operation is complete
  • RFSH. Refresh (output, active Low). RFSH, together with MREQ, indicates that the lower seven bits of the system’s address bus can be used as a refresh address to the system’s dynamic memories.
  • WAIT. input, active Low). WAIT communicates to the CPU that the addressed memory or I/O devices are not ready for a data transfer. The CPU continues to enter a WAIT state as long as this signal is active.
  • WR. Write (output, active Low, tristate). WR indicates that the CPU data bus contains valid data to be stored at the addressed memory or I/O location.
  • CLK. Clock (input). Single-phase MOS-level clock.
  • The Zilog Z80 CPU is a fourth-generation enhanced microprocessor, the internal registers include two sets of six general-purpose registers which can be used individually as either 8-bit registers or as 16-bit register pairs. In addition there are two sets of Accumulator and Flag registers. The Z80 CPU also contains a Stack Pointer, Program Counter, two index registers, a refresh register, and an interrupt register. The CPU only requires a single +5V power source. All output signals are fully decoded and timed to control standard memory or peripheral circuits. This figure shows the internal architecture and major elements of the Z80 CPU.

    z80 block diagram

    The Z80 CPU contains 208 bits of read/write memory that are implemented using static RAM. This memory is configured to eighteen 8-bit registers and four 16-bit registers. The registers include two sets of six general-purpose registers that can be used individually as 8-bit registers or in pairs as 16-bit registers. There are also two sets of Accumulator and Flag registers and six special-purpose registers. The first special purpose register is the Program Counter (PC). The program counter holds the 16-bit address of the current instruction being fetched from memory. The Program Counter is automatically incremented after its contents are transferred to the address lines. When a program jump occurs, the new value is automatically placed in the Program Counter. The second special purpose register is the Stack Pointer (SP). The stack pointer holds the 16-bit address of the current top of a stack located anywhere in the system RAM memory. The stack organized as a last-in first-out (LIFO) file. Data can be pushed onto the stack from specific CPU registers or popped off of the stack to specific CPU registers through the execution of PUSH and POP instructions. The data popped from the stack is always the most recent data pushed onto it.

    z80 registers

    The third pair of special purpose registers are the two Index Registers (IX and IY). The two independent index registers hold a 16-bit base address that is used in indexed addressing modes. In this mode, an index register is used as a base to point to a region in memory from which data is to be stored or retrieved. An additional byte is included in indexed instructions to specify a displacement from this base. The fourth special purpose register is the Interrupt Page Address (I) Register. The Z80 CPU can be operated in a mode in which an indirect call to any memory location can be achieved in response to an interrupt. The I register is used for this purpose and stores the high-order eight bits of the indirect address while the interrupting device provides the lower eight bits of the address. The fifth special purpose register is the Memory Refresh (R) Register. The Z80 CPU contains a memory refresh counter, enabling dynamic memories to be used with the same ease as static memories. Seven bits of this 8-bit register are automatically incremented after each instruction fetch, the data in the refresh counter is sent out on the lower portion of the address bus along with a refresh control signal while the CPU is decoding and executing the fetched instruction. The last pair of special purpose registers are the Accumulator and Flag Registers. The CPU includes two independent 8-bit Accumulators and associated 8-bit Flag registers. The Accumulator holds the results of 8-bit arithmetic or logical operations while the Flag Register indicates specific conditions for 8-bit or 16-bit operations, such as indicating whether or not the result of an operation is equal to zero. The programmer selects the Accumulator and flag pair with a single exchange instruction.

    There are also two sets of General Purpose Registers, each containing six 8-bit registers that can be used individually as 8-bit registers or as 16-bit register pairs. One set is called BC, DE, and HL while the complementary set is called BC', DE', and HL'. At any one time, the programmer can select either set of registers to work through a single exchange command for the entire set. This can be used in and interrupt routine to use the alternate register set and switch back at the end instead of pushing all registers to stack and restoring them afterwards. This is sacrificing a complete set of registers in favor of speed. The Arithmetic Logic Unit can execute 8 bit arithmetic and logical instructions. Internally, the ALU communicates with the registers and the external data bus by using the internal data bus. Functions performed by the ALU include: Add, Subtract, Logical AND, Logical OR, Logical exclusive OR, Compare, Left or right shifts or rotates, Increment, Decrement, Set bit, Reset bit and Test bit.

    Z80 Timing

    The next diagram describes the pins and signal timings the Z80 takes to get data from memory, or store it into memory or IO. These transfer of address and data occurs parallel and is based on how memory chips work with their CS, OE, and WR signals. The image below shows the data, timing and sequence of all pins involved.

    z80 cycles

    When the Z80 is reset it begins by reading the first instruction in memory at address location 0x0000. To fetch the instruction, the Z80 starts by setting the address pins to 0x0000, and then sets M1 to low. On the falling edge of the first clock pulse, the Z80 sets the RD pin to low to indicate that it wants to read data, while the MREQ pin goes low to indicate that the Z80 wants to read data from memory. The next clock cycle, T2, is an extra delay cycle that gives external memory time to produce its output. On the third clock cycle the Z80 reads the data in from the data pins, and on the rising edge of the third clock cycle the Z80 resets the RD and MREQ pins back to high. The data that was read will be an instruction, and the Z80 will either execute the instruction or get more data from memory to complete the instruction.

    When the Z80 wants to write to memory, it first sets the address pins to the location it wants to write to. On the falling edge of the first clock, the MREQ pin is set to low to indicate that it wants to write to memory, and the data pins are set to the data that has to be saved. On the falling edge of the second clock, the Z80 sets the WR pins to low to signal to the I/O device or memory that the data is valid to copy into the memory chip that has been selected. On the falling edge of the third clock cycle, the Z80 sets WR and MREQ to high to indicate the ending of the write cycle.

    In I/O instructions the Z80 does the same, but uses IORQ instead of the MREQ pin.

    As you can see the Z80 processor is very easy in timing and a very friendly CPU to all kind of computer chips. The timing diagrams are also very logic and require a minimal number of external chips to build a complete system. I will not discuss the timing diagrams here, they can be found in the Z80 manual. What I can show is a minimal Z80 system with a CPU some ROM (EPROM) and static RAM memory and a serial I/O port. This minimal system can still be bought for somewhere between 25 and 35 euros. It usually comes with a build in Basic interpreter, but I delete that and the fun part is making your own system from scratch in assembler or ‘C’.

    z80 minimal system schema

    Z80 with atmega chip as I/O and memory

    Because the easy and logical signal timings of the Z80 processor a complete Z80 system can be build using a Atmega processor to emulate the ROM, the RAM, the clock signal and the I/O for the Z80 processor. There are several projects today that use this concept, the easiest one is a simple project using a Z80 processor and an Arduino Mega board. The Arduino Mega board is fast enough to provide the correct I/O timing and emulate a ROM and RAM chip in the internal memory of the Arduino Mega. The Serial I/O is also handled the Arduino Mega, to the Z80 it’s just an I/O port. Just include the Z80 code as hex array in the include file. My Z80 IDE software can generate this ‘C’ style hex array. You can develop test and debug the code in my Z80 IDE and then see the code running on a real Z80 CPU.

    z80 with Arduino Mega

    This is the schema of all the connections of the Z80 pins to the Arduino Mega board I/O pins.

    z80 with Arduino Mega schema

    Beacuse this is a rather fragile solution I build this project on am Arduino Mega experriment shield, using a IC socket for the Z80 and a pin array on both sides to connect the pins of the Z80 to the Arduino Mega pins. I could also use shorter wires and the whole shield is more permanent and reusable.

    z80 with Arduino Mega shield

    You can use the Arduino IDE to upload new Z80 code the Arduino Mega time after time and use the build in terminal as serial I/O of the Z80 processor. You can find the original project, schematics and source code on this site. The project on Arduin project hub.
    And here is anothe project using the same idea: Site of Baltazar Studios.

    Z80 MBC computer board

    Another nice project that’s currently in version 3 is the Z80-MBC project. Currently version 3 is very sophisticated and becoming a real computer, I like the smaller version the Z80-MBC2 and even the original Z80-MBC. Version 2 is a very easy to build Z80 Single Board Computer with a SD as "disk emulator" and with a 128KB banked RAM for CP/M 3 (but it can run CP/M 2.2). It has an optional on board 16x GPIO expander, and uses common cheap add-on modules for the SD and the RTC options. It also has an "Arduino heart" using an Atmega32A as EEPROM and "universal" I/O emulator (like the Arduino Mega board in the above project) although it’s a little harder to find a programmed Atmega32A because this chip can only be programmed using an ISP programmer. But you can buy this computer board as a complete kit on the Internet. You can use the programming tools of CP/M, but this acts more like a real Z80 full computer system. But it is still low cost (around 70 euro) and a nice way to see what programming was like in the “old days”.

    z80 MBC2 board

    You can download and read all the source code, the schematics and build instructions on the project site. Go to project page on website.

    As you can see there is still an active community building nice projects using the good old Z80 CPU. The Z80 CPU and all the chips are still available and the DIL (Dual in line) versions are easy the handle and to solder into a circuit The Z80 was my first love (for a CPU) and it will remain my favorite processor.

    Z80 PIO chip

    In a lot of Z80 based systems you can see the Z80 PIO chip beside the Z80 CPU chip. This chip is basically just a digital parallel I/O port chip. You can configure the individual port pins as digital inputs or outputs and then use them for whatever you want. The A/B input selects between either PortA or PortB and the C/D input selects between either the control register or the data register. The control registers are used to configure the ports and the data registers are used to read/write the actual data. By connecting these to A0 and A1 one can access the desired register using the address bus in an I/O read or write. The least significant bit of the memory address A0 then seledts the port A or B and the A1 line selects between the data and the control registers. With an address decoder you can put this chip anywhere in the I/O addressing space. In a lot of systems this chip was used to add a parallel printer port to the Z80 system. But the chip can also handle digital inputs from switches and can be used to driver signaling LEDs. One of the unique features of the Z80-PlO is that all data transfer between the peripheral device and the CPU can be accomplished under total interrupt control even with nested interrupts. The the PlO can be programmed to interrupt if any specified peripheral alarm conditions should occur. This interrupt capability reduces the amount of time that the processor has to spend in polling peripheral status.You can still buy this chip and it costs only a few dollars.

    The Z80 PIO internal.
    z80 PIO internal

    The Z80 PIO Pins.
    z80 PIO pins

    Link to documentation: z80piomn.pdf Z80 PIO User Manual (Pdf).

    Z80 SIO chip

    Beside the parallel PIO chip there was also a SIO chip for serial communication. Unfortunately this was a complicated chip to program and I do not see it used nowadays. The SIO contains 3x READ ONLY registers for the 'B' channel, 2x READ ONLY registers for the 'A' channel, 8x WRITE registers on the 'B' channel and 7x WRITE registers for the 'A'. Clearly for anyone attempting to make one of these things work correctly, a degree of understanding is needed. The device can be used in polling mode and also in interrupt mode when a character us received or and output buffer is empty. With other registers you can set or read the additional control lines. I never used this device and nowadays there are several alternative chips available.

    The Z80 SIO internal.
    z80 SIO internal

    The S80 PIO Pins.
    z80 SIO pins

    Link to documentation: ps0183.pdf Z80 SIO Manual (Pdf).

    The Z80 actually has a 4-bit ALU

    Z80 processor As you can read on other pages, I am a reasonable fan of the Z80 processor. The Z80 is officially an 8 bit processor but also has registers that can be used as a pair as a 16 bit register. That's why I was surprised to read that the Z80 actually has a 4-bit ALU (Arithmetic logic unit). How that works I try to explain on this page. The makers of the Z80 are already dropping something about this in a interview of the computer history museums. I also think that Ken Shirriff in his blog here excellent explains thie feature.

    Some fanatics have been studying the Z80's silicon to understand the processor's physical layout. The ALU of the Z80 exists of four one-bit ALU units that together form a four-bit ALU. The ALU itself has a 4 bit high bit bus and a four bit low bit bus..

    z80 4bits alu

    An operation starts by loading 2 oparands from the registers to the four bit latches. What I didn't draw here is that bit shift is already happening when loading this operations can be performed. Then via the two four-bit mux (multiplexers) of both op1 and op2 the lowest four bits will pass through the ALU and be stored in the low bit latch. Then the high four bits will be presented to the ALU via the multiplexers and the result is low together with the stored four bits. latch again a 2 x 4 = 8 bit value that can be written back to the result register.

    I have simplified this diagram a bit, in reality there are two shifters between the register bus and the 4 bit buses of the ALU, which both move to can slide left and right and there are inverters for the MUX to simplify calculations. There is also logic for the carry and the other flags in, but since these don't make any difference to the principle, I've left them out. This also explains the so-called half carry of the Z80 processor. The 4 bit ALU can perform operations on two times four bits such as addition, subtraction, logical AND / OR and XOR. Together with the bit shifters, this allows all operations are performed. This also explains why certain operations also cost so many cycles.

    Why did they choose a 4 bit CPU instead of a full 8 bit CPU? The first reason I could think of is a simpler design, but if you think carefully this will not really be the case. The real reason is in the interview. Since both designers came from Intel and the 8080 had worked and the Z80 would be byte compatible (and thus a direct replacement without code changes) were lawsuits from Intel lurking of course. So it was important to make a design that would deviate so much from the 8080 design, but with exactly the same functionality. Some changes in the design of the transistors on the silicon were just real improvements but the structure of the CPU was so completely different so this was a deliberate action to avoid lawsuits from Intel.

    Conversely, Zilog also ran the risk that companies such as NEC would copy their new processor and for that, silicon design a number of "traps". These were transitors that had no function or affect the design, but were only meant to make reverse engineering more difficult. Apparently NEC later admitted that they were delayed by six months because of these traps.

    There was one thing that Intel really had a patent on and that was the set of menomics (short for the names of the instructions) so Zilog had to build a completely new set of instruction names. Intel later carried over their instruction names in all new processors and so did Zilog. This was sometimes difficult for programmers, especially when one had to program for both the 8080 and the Z80. I had to do this myself too. But since I have processors for many differences programmed in assembler I learned to keep the different sets of instructions apart.

    Freeware Z80 IDE

    HTTP Health monitor To be able to program for the z80 you need an assembler or compiler. I personally still like to write in Z80 assembler but I could no longer find tools for Windows 10. There were still some programs to download but most of them worked at DOS level. After some searching I decided that it was time for a new hobby project, building a complete integrated Z80 development environment. I found a pretty good assembler and good portable C code from an emulator and the rest I had somewhere in my code library. The result is Z80 workbench, a portable x64 Windows program that includes an editor, assembler, disassembler, emulator, single step debugger, Intel hex read / write function a terminal window, an MPF-1 compatible seven segment display with 8 LEDs and keyboard support. One of the unique features of the Z80-PlO is that all data transfer between the peripheral device and the CPU can be accomplished under total interrupt control even with nested interrupts. The the PlO can be programmed to interrupt if any specified peripheral alarm conditions should occur. This interrupt capability reduces the amount of time that the processor has to spend in polling peripheral status.
    Download the program on this page

    Z80 related documents

    Z80 links, tips and webpages

    My first real Z80 computer the TRS80 Model 1

    This was my first real computer back in the 80ties and I wrote a lot software for this computer in basic but also a lot in assembler. I expanded the memory myself by piggybacking the 64K dynamic RAM chips on top of the 16K versions and I expanded the video circuit to lowercase as well. I did several other upgrades and by the time I switched to a Sinclair spectrum the TRS80 was full of wires and mods, but still running fine. I lost that computer in one of the moves I did to another house, it is still sad I lost it. Using this computer I learned the Z80 processor inside out.

    • Name: TRS 80 Model I
    • Company: Tandy Radio Shack
    • Made in: U.S.A.
    • Year: 1977
    • Basic: Level II (12k ROM models)
    • Keyboard: Full 53 keys
    • CPU: Zilog Z80 / 1.77 MHz
    • RAM: 4 kb / 16 kb
    • VRAM: 1 kb
    • ROM: 12kb (Basic Level 2)
    • Textmode: 32 x 16 of 64 x 16
    • Graphics: 128 x 48 pixels
    • Color: None (B/W)
    • Sound: None
    • I/O: Monitor, cassette interface, expansion port

    TRS80 Model 1 documents

    Last update: 11-12-2021

    Disclaimer: All pages on this Web site are copyrighted by Hein Pragt, unless otherwise noted. I strive for accuracy but cannot be held responsible for any errors in the content. For questions about the content of this site or persmission to copy you can contact me at: (email: is registered under KvK number: 73839426.